Regulation/bypass automation for LDO with multiple supply voltages

ABSTRACT

Regulation/Bypass automation for a low drop-out regulator (LDO) with multiple supply voltages is disclosed. In some implementations, a LDO includes a resistor, a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to a first terminal of the resistor; a feedback switch having a drain, a gate, and a source, the drain coupled to a second terminal of the resistor, the source coupled to a negative input of the OTA; and an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.

FIELD OF DISCLOSURE

Aspects of the present disclosure relate generally to power regulation in semiconductor circuits, and more particularly to regulation/bypass automation for low drop-out regulator (LDO) with multiple supply voltages.

BACKGROUND

As semiconductor technology advances, many systems on a chip (SoCs) can operate at lower voltage supply (e.g., 1.8V), resulting in lower overall power consumption. However, the need to support legacy devices that operate at higher voltage supplies (e.g., 5V, 3.3V, etc.) remains. Therefore, there is a need in the art to provide a more flexible and efficient LDO to allow advance process SoCs to support legacy devices.

SUMMARY OF THE DISCLOSURE

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all implementations. The sole purpose of this summary is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

In some implementations, a low drop-out regulator (LDO) includes a first resistor having a first terminal and a second terminal; and a p-type pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to the first terminal of the first resistor. The LDO further includes a p-type feedback switch having a drain, a gate, and a source, the drain coupled to the second terminal of the first resistor, the source coupled to a positive input of the OTA. The LDO further includes an n-type pull-down transistor having a drain, a gate, and a source, the source coupled to ground, the gate coupled to the gate of the p-type feedback transistor, and the drain coupled to the negative input of the OTA, wherein the gate of the n-type pull-down transistor and the gate of the p-type feedback switch are configured to receive a bypass signal.

In some implementations, the LDO further includes a second resistor having a first terminal and a second terminal. The second terminal is coupled to ground and the first terminal is coupled to the second terminal of the first resistor.

In some implementations, the bypass signal is asserted when the supply voltage is at approximately 1.8V. The bypass signal can be de-asserted when the supply voltage is at 3.3V or 5.0 V. The LDO enters a bypass mode when the bypass signal is asserted. On the other hand, the LDO enters a regulation mode when the bypass signal is de-asserted.

In some implementations, the LDO operates in the regulation mode by default when the LDO is powered on.

To the accomplishment of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the description embodiments are intended to include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram of one implementation of a low drop-out regulator (LDO) in a system on a chip (SoC).

FIG. 2 illustrates a conventional LDO in a SoC.

FIG. 3 shows a detailed circuit implementation of one conventional LDO.

FIG. 4 shows a waveform diagram to illustrate the potential “glitch” at power on that can cause reliability problem.

FIG. 5A shows one implementation of a LDO.

FIG. 5B shows one implementation of a SoC.

FIG. 6 shows one exemplary power-on sequence of SoC illustrated in FIG. 5B.

FIG. 7 shows one exemplary method of operating LDO 520 shown in FIG. 5A.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

System on a chip (SoC) design in advanced technology node needs to interface with multiple input/output (I/O) voltage supplies, including higher voltages in legacy devices. A uniform power-on sequence for various I/O supplies is a must-have feature for power management unit (PMU) to shorten product development time. A regulator, typically, a low drop-out regulator (LDO), is needed to lower the I/O voltage supply when interfacing with legacy products or bypass I/O voltage supply when the I/O voltage supply is about the same as in the SoC. In other words, a normal mode (a.k.a. a regulation mode) and a bypass mode are needed in today's SoC designs as conceptually illustrated in FIG. 1.

FIG. 1 is a conceptual diagram of one implementation 100 of a low drop-out regulator (LDO) in a system on a chip (SoC). On the left side of arrow 140, three use cases 110-130 are illustrated. In use case 110, Customer A represents a legacy device that operates at 5 V. In use case 120, Customer B represents another legacy device that operates at 3.3V. In use case 130, Customer C represents a device that operates at 1.8V. In the current example, the SoC operates at 1.8V. Therefore, to support Customer A, the SoC needs a LDO 112 that converts an I/O voltage supply of 5V to 1.8V. Likewise, to support Customer B, the SoC needs a LDO 122 that converts an I/O voltage supply of 3.3V to 1.8V. Because Customer C already operates at 1.8V, which is the same as the SoC, the SoC does not need any voltage regulator to support Customer C. In other words, the SoC can bypass the LDO when supporting Customer C (a.k.a. a bypass mode). To enhance the flexibility and versatility of the SoC, the LDOs 112 and 122, as well as the bypass mode represented in use case 130, are combined into a LDO that supports multiple supply voltages and automatically switches between regulation mode and bypass mode in some implementations.

In some advanced technology nodes, high voltage (HV) devices are used to interface with legacy high I/O supply voltage. Though the drain source voltage (Vds) range of the HV devices is increased, gate source voltage (Vgs) is still limited (e.g., Vgs has to be equal to or below 1.8V in 28 nm node). Internal logic level has to be 1.8V even if I/O supply voltage is at a higher level (e.g., 5 V, 3.3 V), or 1.8V in the example shown in FIG. 1, for reliability reason.

One conventional SoC design 200 is shown in FIG. 2. A supply detector 210 is used to detect the voltage level of the voltage supply received from a customer device A, B, or C, and then to send out a logic signal to configure LDO 220 in regulation mode or bypass mode (as represented by the diode connected p-type transistor 225) based on the voltage supply detected. However, the logic circuit 212 in the supply detector 210 typically requires a 1.8V voltage supply from the output of LDO 220 in order to be powered up and function correctly. But at boot up, the output of LDO 220 may not be at 1.8V yet. This can cause a chicken-and-egg issue in the power on sequence of the SoC design 200.

Another issue with the SoC design 200 in FIG. 2 is the reliability problem. If LDO 220 is in bypass mode at first for an I/O supply voltage at 5V or 3.3V, Vgs of the diode connected p-type transistor 225 may go beyond 1.8V. Such high Vgs on the transistor 225 may put too much stress on the transistor 225 and results in reliability problem later in the lifetime of the SoC 200. For instance, transistor 225 may eventually break down over a prolonged period of use, leading to malfunctioning of LDO 220.

FIG. 3 shows a detailed circuit implementation of one conventional LDO 320 used in a SoC. LDO 320 includes a pair of n-type transistors 321 and 322, a bias transistor 325, a pair of p-type transistors 323 and 324, a pass transistor (a.k.a. a pass switch) 326, an n-type transistor 327, a switch 328, a pair of output resistors 329 a and 329 b, an output capacitor 332 and a capacitor 331. In some implementations, the aforementioned transistors of LDO 320 are all HV devices. Transistors 321 and 322 are configured as negative and positive input transistors, respectively. The source of each of transistors 321 and 322 are coupled to a drain of the bias transistor 325. A source of the bias transistor 325 is coupled to ground. The drains of the input transistors 321 and 322 are coupled to the drains of transistors 323 and 324, respectively. The gates of transistors 323 and 324 and the drain of transistor 323 are coupled together. The sources of transistors 323 and 324 are coupled to a voltage supply VddH from a device external to the SoC. In the case of a legacy device (e.g., Customer A or Customer B in FIG. 1), the voltage supply VddH can be at 5V or 3.3V. In the case of a low power device (e.g., Customer C), the voltage supply VddH can be at 1.8V. Transistor 324 is coupled in parallel to capacitor 331. The drain of transistor 324 is coupled to the gate of pass transistor 326 and the drain of transistor 327. The source of transistor 327 is coupled to ground. The gate of transistor 327 receives a bypass signal 301 from a voltage comparator. The source of the pass transistor 326 is coupled to voltage supply VddH and the drain of the pass transistor 326 is coupled to output resistor 329 a and output capacitor 332. Output resistors 329 a and 329 b are coupled in series between transistor 326 and ground, while output capacitor 332 is coupled in parallel to output resistors 329 a and 329 b.

A switch 328 is coupled between the gate of pass transistor 326 and the drain of transistor 324 to switch between the regulation or bypass modes. However, as discussed above, in advanced process nodes (e.g., 28 nm or beyond), 3.3V/0V voltage cannot be applied to the switch 328 due to reliability concern. FIG. 4 shows a waveform diagram 400 to illustrate the potential “glitch” at power up that can cause reliability problem. As shown n FIG. 4, there is a glitch 410 in the bypass signal and vdd18 during power ramp-up. This glitch 410 can lead to reliability problem in pass transistor 326. Specifically, if supply voltage VddH is at 5V or 3.3V and bypass signal is at 1.8V, then the source gate voltage (Vsg) of pass transistor 326 will exceed 1.8V, leading to reliability fail. Thus, a LDO is needed to address the power-on sequence issue and the reliability issue discussed above. Some implementations of such a novel LDO are disclosed herein.

In some implementations, the LDO can automate regulation or bypass dual mode function for 1.8V I/O voltage delivery during power-on event to support legacy I/O voltages at 5V or 3.3V (e.g., Customers A and B, respectively, in FIG. 1), as well as 1.8V I/O voltage required by many current devices (e.g., Customer C in FIG. 1). The LDO can enter regulation mode with close-loop operation when a bypass signal is at logical “0”, and the LDO can enter bypass mode with open-loop option when the bypass signal is at logical “1”. In some implementations, the bypass signal is a 1.8V logic signal and it can come from comparators which run at 1.8V from the LDO. In this regard, there is a “chicken-and-egg” problem for the LDO and the comparators to handle the bypass signal. Some implementations of a novel LDO disclosed herein can mitigate this “chicken-and-egg” problem while addressing the reliability and power-up sequence issues discussed above.

FIG. 5A illustrates implementation of the LDO 520 and FIG. 5B illustrates one implementation of a SoC 500 incorporating the LDO 520 in FIG. 5A.

Referring to FIG. 5A, LDO 520 includes a pair of n-type transistors 521 and 522, a bias transistor 525, a pair of p-type transistors 523 and 524, a pass transistor (a.k.a. a pass switch) 526, a pair of output resistors 529 a and 529 b, an output capacitor 532 and a capacitor 531. In some implementations, the aforementioned transistors of LDO 520 are all HV devices. Transistors 521 and 522 are configured as negative and positive input transistors, respectively. The source of each of transistors 521 and 522 are coupled to a drain of the bias transistor 525. A source of the bias transistor 525 is coupled to ground. The drains of the input transistors 521 and 522 are coupled to the drains of transistors 523 and 524, respectively. The gates of transistors 523 and 524 and the drain of transistor 523 are coupled together. The sources of transistors 523 and 524 are coupled to a voltage supply VddH from a device external to the SoC. In the case of a legacy device (e.g., Customer A or Customer B in FIG. 1), the voltage supply VddH can be at 5V or 3.3V. In the case of a low power device (e.g., Customer C), the voltage supply VddH can be at 1.8V. Transistors 521-525 together are configured as an operational transconductance amplifier (OTA), where the gates of transistors 521 and 522 serve as the negative and positive input terminals, respectively, of the OTA. The drain of transistor 524 can be configured as an output of the OTA.

In some implementations, transistor 524 is coupled in parallel to capacitor 531. The drain of transistor 524 is coupled to the gate of pass transistor 526. The source of pass transistor 526 is coupled to voltage supply VddH and the drain of the pass transistor 526 is coupled to output resistor 529 a and output capacitor 532. Output resistors 529 a and 529 b are coupled in series between pass transistor 526 and ground, while output capacitor 532 is coupled in parallel to output resistors 529 a and 529 b.

In some implementations, at least two more transistors 542 and 544 are added to the feedback path between output resistor 529 a and the gate of transistor 521 (i.e., the negative input terminal of the OTA). Transistor 542 may be referred to as a feedback switch or feedback transistor, whereas transistor 544 may be referred to as a pull-down switch or pull-down transistor. Referring to FIG. 5A, transistor 542 is a p-type transistor having a gate, a source, and a drain. Transistor 544 is an n-type transistor having a gate, a source, and a drain. The gates of both transistor 542 and 544 are coupled together to receive a bypass signal 501. The source of transistor 544 is coupled to ground. The drain of transistor 544 is coupled to the gate of transistor 521. The source and the bulk of transistor 542 are coupled together, which is further coupled to the gate of transistor 521. The drain of transistor 542 is coupled to a node in between output resistor 529 a and output resistor 529 b.

LDO 520 can go into bypass mode when supply voltage VddH is at 1.8V, or regulation mode when supply voltage VddH is at 5V or 3.3V. In some implementations, LDO 520 is configured into one of the bypass mode or regulation mode in response to bypass signal 501. When bypass signal 501 is at a logical “0”, transistor 542 is turned on to close the feedback loop, resulting in an output of 1.8V at the drain of pass transistor 526. Thus, LDO 520 goes into regulation mode. When bypass signal 501 is at a logical “1”, transistor 542 is turned off to open (or break) the feedback loop, and transistor 544 is turned on to pull the gate of transistor 521 to ground. Thus, LDO 520 goes into bypass mode.

LDO 520 can work with a number of infrastructural blocks in a SoC to support customer devices requiring different voltage supplies. One implementation of a SoC 500 having LDO 520 and other infrastructural blocks is shown in FIG. 5B. Referring to FIG. 5B, SoC 500 includes a bypass comparator 510, a bandgap reference generator 512, a resistor divider 514, a V-to-IR (V2IR) block 516, an OK detector 518, and LDO 520.

In some implementations, a voltage supply VddH from a customer device external to SoC 500 is input to bandgap reference generator 512, resistor divider 514, V2IR block 516, and LDO 520. As discussed above, the voltage supply can be at 5 V or 3.3V for legacy customer devices, or 1.8V for current customer devices. Bandgap reference generator 512 is configured to output a bandgap voltage vbg at about 1.23V. The signal vbg remains substantially constant at about 1.23V when voltage supply VddH is available. The signal vbg is then input to V2IR 516 and LDO 520. Resistor divider 514 is configured to divide voltage supply VddH received with about 0.3 ratio to produce a signal vddhdiv, which can be at about 1.5V, 0.99V, or 0.54V if VddH is at 5V, 3.3V, or 1.8V, respectively. Using combinations of on-chip resistors within V2IR 516, V2IR 516 is configured to convert vbg into IR currents that translate into three voltage signals, namely, v1 p 23 at about 1.23V, v0 p 9 at about 0.9V, and v0 p 74 at about 0.74V. These three voltage signals are also substantially constant when both VddH and vbg are available. The signal v0 p 9 is then input to Ok detector 518, and the signal v0 p 74 is input to a positive input terminal of bypass comparator 510. A negative input terminal of bypass comparator 510 receives vddhdiv from resistor divider 514. Bypass comparator 510 outputs bypass signal 501. LDO 520 also receives vbg (which is at about 1.23V) from bandgap reference generator 512. LDO 520 further receives bypass signal 501 output from bypass comparator 510. As discussed above with reference to FIG. 5A, LDO 520 generates an output voltage vdd18 of about 1.8V. LDO 520 provides the output voltage of 1.8V to both Ok detector 518 and bypass comparator 510. Ok detector 518 detects v0 p 9 voltage level and asserts an ok_mbg signal, which is input to an enable input terminal of bypass comparator 510. Bypass comparator 510 compares vddhdiv against v0 p 74 when ok_mbg is asserted and outputs bypass signal 501 accordingly.

One exemplary power-on sequence of SoC 500 is shown in FIG. 6. During cold boot of SoC 500, the external voltage supply VddH ramps up first before the internal voltages are ready for voltage detection or conversion. The default setting for ok_mbg and bypass 501 is at logical “0” and LDO 520 initially operates in the closed-loop mode (i.e., the regulation mode). In other words, the bypass signal 501 is de-asserted initially and LDO 520 operates in the regulation mode by default when LDO 520 is powered on. The bandgap voltage vbg ramps up slowly and the derived internal reference voltages (i.e., v1 p 23, v0 p 9, and v0 p 74 from V2IR 516) come after vbg with similar slow ramp. The output from LDO 520 (i.e., vdd18) keeps track of these three references and vdd18 remains at 1.8V from input vbg. Since ok_mbg is generated by Ok detector 518, which is supplied by vdd18, the voltage level of ok_mbg tracks vdd18. By the time ok_mbg reaches the threshold voltage level of logical “1”, the internal voltage references (i.e., v1 p 23 at 1.23V, v0 p 9 at 0.9V, and v0 p 74 at 0.74V) are ramped up and ready, and thus, bypass comparator 510 starts to detect VddH voltage level and take control of the bypass signal 501. At this point, if voltage supply VddH is at 1.8V, bypass signal 501 will be asserted, and the feedback node of LDO 520 (i.e., the node to which the gate of input transistor 521 is coupled to in FIG. 5A) is pulled to ground, i.e., 0V, which breaks the feedback loop and bypasses the 1.8V to the output of LDO 520, i.e., vdd18. On the other hand, if voltage supply VddH is at 3.3V or 5V, bypass signal 501 is de-asserted and LDO 520 keeps regulating 1.8V for the output of LDO 520, i.e., vdd18. This automation can solve the reliability problem of using HV/1.8V devices for legacy customer devices that requires high I/O voltage (e.g., 3.3V or 5V) discussed above.

In addition to solving the reliability problem, the architecture of LDO 520 also provides the following advantages. First, the architecture of LDO 520 is not limited to three external power supply voltages. More threshold voltages can be added in to detect more external power supply voltages. Further, the external power supply voltage range can be wider in some implementations, e.g., 2.1V-5V/1.8V and can generate 1.8V internal power supply if low threshold is set to about 0.59V and the saturation voltage Vdsat of LDO pass transistor (e.g., transistor 526 in FIG. 5A) is at 300 mV. This provides more flexibility to customers. Moreover, the internal power supply voltage is also flexible, as it can be adjusted to be more or less than 1.8V, depending on internal circuit specification.

FIG. 7 shows a flow diagram of one exemplary method of operating LDO 520 shown in FIG. 5A. The method begins at block 710, where LDO 520 receives a bypass signal (e.g., bypass signal 501 in FIG. 5A). Then the method transitions to block 720 to determine if bypass signal is asserted. If bypass signal is asserted, the method transitions to block 730, where a feedback switch (e.g., feedback switch 542) between a feedback node and an output resistor in LDO 520 is turned off. Then the method transitions to block 740, in which the feedback node is pulled to ground to open (or break) a feedback loop within LDO 520. In other words, LDO 520 goes into bypass mode when bypass signal is asserted.

If it is determined that bypass signal is not asserted at block 720, then the method transitions to block 750. At block 750, the feedback switch is turned on to close the feedback loop in LDO 520 to cause LDO 520 to generate a regulated output voltage, e.g., a regulated 1.8V. In other words, LDO 520 goes into regulation mode when bypass signal is de-asserted.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. 

What is claimed is:
 1. A low drop-out regulator (LDO), comprising: a first resistor having a first terminal and a second terminal; a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to the first terminal of the first resistor; a feedback switch having a drain, a gate, and a source, the drain coupled to the second terminal of the first resistor, the source coupled to a negative input of the OTA; and an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, the gate coupled to the gate of the feedback switch, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.
 2. The LDO of claim 1, further comprising: a second resistor having a first terminal and a second terminal, the second terminal coupled to ground and the first terminal coupled to the second terminal of the first resistor.
 3. The LDO of claim 1, wherein the bypass signal is asserted when the supply voltage is at approximately 1.8V.
 4. The LDO of claim 3, wherein the LDO enters a bypass mode when the bypass signal is asserted.
 5. The LDO of claim 4, wherein, in response to the bypass signal being asserted, the pull-down transistor pulls the negative input of the OTA to ground.
 6. The LDO of claim 1, wherein the bypass signal is de-asserted when the supply voltage is at approximately 3.3V or 5.0V.
 7. The LDO of claim 6, wherein the LDO enters a regulation mode when the bypass signal is de-asserted.
 8. The LDO of claim 7, wherein, in response to the bypass signal being de-asserted, the feedback switch is closed to cause the pass transistor to output a regulated voltage at approximately 1.8V.
 9. The LDO of claim 1, wherein the supply voltage is within a range of approximately 5V to 1.8V.
 10. The LDO of claim 1, wherein the feedback switch comprises a first p-type transistor, the pull-down transistor is an n-type transistor, and the pass transistor is a second p-type transistor. 